@mchp-mcc/main-core NPM

MCC Melody Main Core PLIB

Overview

Main Core allows the user to make MSI configurations and ICD pin selection.It is available only in multi core devices.

MSI module is a bridge between the Main and a Secondary processor system, each of which operates within independent clock domains

The Main and Secondary have their own registers to communicate between the MSI modules; the Main MSI registers are located in the Main SFR space and the Secondary MSI registers are in the Secondary SFR space.

Documentation link

https://onlinedocs.microchip.com/v2/keyword-lookup?keyword=MSI_USER_GUIDE&version=latest&redirect=true

Features

MSI in Melody supports the following features

Sixteen Unidirectional Data Mailbox Registers
- Direction of each Mailbox register is fuse-selectable
- Byte and word-addressable
- Eight Mailbox Data Flow Control Protocol Blocks
- Individual fuse enables
- Write port active; read port passive (i.e., no read data request required)
- Automatic, interrupt-driven (or polled), data flow control mechanism across MSI clock boundary
- Fuse assignable to any of the Mailbox registers, supports any length data buffers (up to the number of available Mailbox registers)
- Interrupt-based, software polled or DMA transfer-compatible
Main to Secondary and Secondary to Main Interrupt Request with Acknowledge Data Flow Control
Two-Channel FIFO Memory Structure
- One read and one write channel, each 32 words deep
- Circular operation with empty and full status, and interrupts
- Overflow/underflow detection with interrupts to main core and secondary core
- Interrupt-based, software polled or DMA transfer-compatible
Main and Secondary Processor Cross-Boundary Control and Status
- Readable operating mode status for both processors
- Secondary enable from Main (subject to satisfying a hardware write interlock sequencer)
- Main interrupt when Secondary is reset during code execution
- Secondary interrupt when Main is reset during code execution
Optional (fuse) Decoupling of Main and Secondary Resets; POR/BOR/MCLR always Resets Main and Secondary; Influence of Remaining Run-Time Resets on the Secondary Enable is Fuse-Programmable

Changelog

All notable changes to this project will be documented in this file.

1.2.0 - 2023-09-29

New Features

CC16SCRIP-7640 :- Added support to show Main Core for dsPIC33CH1024MP712S1 Secondary device family
CC16SCRIP-7627 :- Showing only relevant ports for dsPIC33CH1024MP712 device family