@mchp-mcc/secondary-core NPM

MCC Melody Secondary Core PLIB

Overview

Secondary Core allows the user to make the required configuration for the secondary device and it is available only in multi core devices.

MSI module is a part of secondary core and it is a bridge between the Main and a Secondary processor system, each of which operates within independent clock domains.

The Main and Secondary have their own registers to communicate between the MSI modules; the Main MSI registers are located in the Main SFR space and the Secondary MSI registers are in the Secondary SFR space.

Documentation link

https://onlinedocs.microchip.com/v2/keyword-lookup?keyword=MSI_USER_GUIDE&version=latest&redirect=true

Features

Secondary core allows the user to configure the following secondary device settings
- Clock
- MSI
- ICD
- Watchdog Timer
- Deadman Timer
- Alternate I2C Pin Mapping
- SPI Pin Mapping
- Context Interrupts
- Assigning Pin Ownership for all available pins
MSI in Melody supports the following features
- Sixteen Unidirectional Data Mailbox Registers
  - Direction of each Mailbox register is fuse-selectable
  - Byte and word-addressable
  - Eight Mailbox Data Flow Control Protocol Blocks
  - Individual fuse enables
  - Write port active; read port passive (i.e., no read data request required)
  - Automatic, interrupt-driven (or polled), data flow control mechanism across MSI clock boundary
  - Fuse assignable to any of the Mailbox registers, supports any length data buffers (up to the number of available Mailbox registers)
  - Interrupt-based, software polled or DMA transfer-compatible
- Main to Secondary and Secondary to Main Interrupt Request with Acknowledge Data Flow Control
- Two-Channel FIFO Memory Structure
  - One read and one write channel, each 32 words deep
  - Circular operation with empty and full status, and interrupts
  - Overflow/underflow detection with interrupts to main core and secondary core
  - Interrupt-based, software polled or DMA transfer-compatible
- Main and Secondary Processor Cross-Boundary Control and Status
  - Readable operating mode status for both processors
  - Secondary enable from Main (subject to satisfying a hardware write interlock sequencer)
  - Main interrupt when Secondary is reset during code execution
  - Secondary interrupt when Main is reset during code execution
- Optional (fuse) Decoupling of Main and Secondary Resets; POR/BOR/MCLR always Resets Main and Secondary; Influence of Remaining Run-Time Resets on the Secondary Enable is Fuse-Programmable